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元器件交易网
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XC1701L
(3.3V),
XC1701
(5.0V) and
?
XC17512L
(3.3V)
Serial Con?guration PROMs
December 10, 1997 (Version 1.1)
05*
Product Specification
FeaturesDescription
?On-chip address counter, incremented by each risingThe XC1701L, XC1701 and XC17512L serial con?guration
edge on the clock inputPROMs (SCPs) provide an easy-to-use, cost-effective
?Simple interface to the FPGA; requires only one usermethod for storing Xilinx FPGA con?guration bitstreams.
IO pin
?Cascadable for storing longer or multiple bitstreams
When the FPGA is in master serial mode, it generates a
?Programmable reset polarity (active High or active Low)
con?guration clock that drives the SCP. A short access time
for compatibility with different FPGA solutions
after the rising clock edge, data appears on the SCP DATA
?Supports XC4000EXXL fast con?guration mode (15.0
output pin that is connected to the FPGA DIN pin. The
MHz)
FPGA generates the appropriate number of clock pulses to
?Low-power CMOS Floating Gate process
complete the con?guration. Once con?gured, it disables the
?Available in 5 V and 3.3 V versions
SCP. When the FPGA is in slave mode, the SCP and the
?Available in compact plastic packages: 8-pin PDIP,
FPGA must both be clocked by an incoming signal.
20-pin SOIC, and 20-pin PLCC.
Multiple devices can be concatenated by using theCEO
?Programming support by leading programmer
output to drive theCE input of the following device. The
manufacturers.
clock inputs and the DATA outputs of all SCPs in this chain
?Design support using the Xilinx Alliance and
are interconnected. All devices are compatible and can be
Foundation series software packages.
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design ?le into a standard Hex format, which is then trans-
ferred to the programmer.
V
CC
V
PP
GND
CE
CEO
RESET
OE or
OE
RESET
CLK
Address Counter
TC
EPROM
OE
Cell
Output
Matrix
DATA
X3185
Figure 1: Simpli?ed Block Diagram (does not show programming circuit)
December 10, 1997 (Version 1.1)5-1

元器件交易网
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Con?guration PROMs
Pin Description
DATA
Data output, 3-stated when eitherCE orOE are inactive.
During programming, the DATA pin is IO. Note thatOE can
be programmed to be either active High or active Low.
Serial PROM Pinouts
Pin Name
DATA
CLK
RESETOE (OERESET)
CE
GND
CEO
V
PP
V
CC
8-Pin
PDIP
1
2
3
4
5
6
7
8
20-Pin
SOIC
1
3
8
10
11
13
18
20
20-Pin
PLCC
2
4
6
8
10
14
17
20
CLK
Each rising edge on the CLK input increments the internal
address counter, if bothCE andOE are active.
RESETOE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESETOE or OERESET. To
avoid confusion, this document describes the pin as
RESETOE, although the opposite polarity is possible on all
devices. When RESET is active, the address counter is
held at zero, and the DATA output is 3-stated. The polarity
of this input is programmable. The default is active High
RESET, but the preferred option is active LowRESET,
because it can be driven by the FPGA’sINIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx HW-
130 Programmer. Third-party programmers have different
methods to invert this pin.
Capacity
Device
XC1701L
XC1701
XC17512L
Con?guration Bits
1,048,576
1,048,576
524,288
Number of Con?guration Bits, Including
Header for all Xilinx FPGAs and Compatible
SCP Type
Device
XC4010XL
XC4013XL
XC4020E
XC4020XL
XC4025E
XC4028XL
XC4028EX
XC4036EX
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Con?guration Bits
283,424
393,623
329,312
521,880
422,176
668,184
668,184
832,528
832,528
1,014,928
1,215,368
1,433,864
1,924,992
SPROM
XC17512L
XC17512L
XC1701
XC17512L
XC1701
XC1701L
XC1701
XC1701
XC1701L
XC1701L
XC1701L +
XC17256L
XC1701L +
XC17512L
2 x XC1701L
CE
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into low-I
CC
standby mode.
CEO
Chip Enable output, to be connected to theCE input of the
next SCP in the daisy chain. This output is Low when the
CE andOE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will followCE as long asOE is active. WhenOE goes
inactive,CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
V
PP
Programming voltage. No overshoot above the speci?ed
max voltage is permitted on this pin. For normal read oper-
ation, this pin
must
be connected to V
CC
. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging.
Do not leave
VPP ?oating!
V
CC
and GND
Positive supply and ground pins.
5-2December 10, 1997 (Version 1.1)

元器件交易网
Controlling Serial PROMs
internal address and bit counters which are incremented on
Most connections between the FPGA device and the Serial
every valid rising edge of CCLK.
PROM are simple and self-explanatory.
If the user-programmable, dual-function DIN pin on the
?The DATA output(s) of the of the Serial PROM(s) drives
FPGA is used only for con?guration, it must still be held at
the DIN input of the lead FPGA device.
a de?ned level during normal operation. The XC3000 and
?The master FPGA CCLK output drives the CLK input(s)
XC4000 families take care of this automatically with an on-
of the Serial |601599 PROM(s).
chip default pull-up resistor.
?TheCEO output of a Serial PROM drives theCE input
of the next Serial PROM in a daisy chain (if any).
Programming the FPGA With Counters
?TheRESETOE input of all Serial PROMs is best driven
Unchanged Upon Completion
by theINIT output of the XC3000 or XC4000 lead
When multiple FPGA-con?gurations for a single FPGA are
FPGA device. This connection assures that the Serial
stored in a Serial Con?guration PROM, theOE pin should
PROM address counter is reset before the start of any
be tied Low. Upon power-up, the internal address counters
(re)con?guration, even when a recon?guration is
are reset and con?guration begins with the ?rst program
initiated by a V
CC
glitch. Other methods – such as
stored in memory. Since theOE pin is held Low, the
drivingRESETOE fromLDC or system reset – assume
address 股票600212 counters are left unchanged after con?guration is
that the Serial PROM internal power-on-reset is always
complete. Therefore, to reprogram the FPGA with another
in step with the FPGA’s internal power-on-reset, which
program, the DP line is pulled Low and con?guration
may not be a safe assumption.
begins at the last value of the address counters.
?TheCE input of the lead (or only) Serial PROM is driven
This method fails if a user appliesRESET during the FPGA
by the DONEPRGM or DONE output of the lead FPGA
con?guration process. The FPGA aborts the con?guration
device, provided that DONEPRGM is not permanently
and then restarts a new con?guration, as intended, but the
grounded. Otherwise,LDC can be used to driveCE, but
Serial PROM does not reset its address counter, since it
must 兴发集团股吧 then be unconditionally High during user
never saw a High level on itsOE input. The new con?gura-
can also be permanently tied Low, but
tion, therefore, reads the remaining data in the PROM and
this keeps the DATA output active and causes an
interprets it as preamble, length count etc. Since the FPGA
unnecessary supply current of 10 mA maximum.
is the master, it issues the necessary number of CCLK
FPGA Master Serial Mode Summary
pulses, up to 16 million (24) and DP goes High. However,
the FPGA con?guration will be completely wrong, with
The IO and logic functions of the Logic Cell Array and their
potential contentions inside the FPGA and on its output
associated interconnections are established by a con?gu-
pins. This method must, therefore, never be used when
ration program. The 南钢股份股吧 program is loaded either automatically
there is any chance of external reset during con?guration.
upon power up, or on command, depending on the state of
the three FPGA mode pins. In Master Mode, the FPGA
Cascading Serial Con?guration PROMs
automatically loads the con?guration program from an
For multiple FPGAs con?gured as a daisy-chain, or for
external memory. The Serial Con?guration PROM has
future FPGAs requiring larger con?guration memories, cas-
been designed for compatibility with the Master Serial
caded SCPs provide additional memory. After the last bit
Mode.
from the ?rst SCP is read, the next clock signal to the SCP
Upon power-up or recon?guration, an FPGA enters the
asserts itsCEO output Low and disables its DATA line. The
Master Serial Mode whenever all three of the FPGA 四川成渝股吧 mode-
second SCP recognizes the Low level on itsCE input and
select pins are Low (M0=0, M1=0, M2=0). Data is read from
enables its DATA output. SeeFigure2.
the Serial Con?guration PROM sequentially on a single
After con?guration is complete, the address counters of all
data line. Synchronization is provided by the rising edge of
cascaded SCPs are reset if the FPGARESET pin goes
the temporary signal CCLK, which is generated during con-
Low, assuming the SCP reset polarity option has been
?guration.
inverted.
Master Serial Mode provides a simple con?guration inter-
To reprogram the FPGA with another program, the DP line
face. Only a serial data line and two control lines are
goes Low and con?guration begins where the address
required to con?gure an FPGA. Data from the Serial Con-
counters had stopped. In this case, avoid 美国股灾 contention
?guration PROM is read sequentially, accessed via the
between DATA and the con?gured IO use of DIN.
December 10, 1997 (Version 1.1)5-3

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